The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating fin structures that form the semiconducting channel in vertical transistor structures, fin field-effect-transistor (finFET) structures, BEOL vertical metallization structures, and the like, on semiconductor chips.
Fin field-effect transistor (finFET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. A finFET device can be built on a semiconductor substrate, where a semiconductor material, such as silicon, is patterned into a fin-like shape and functions as the channel of the transistor. Known finFET devices include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to the semiconductor substrate) between source/drain regions at opposite ends of the fins in the horizontal direction.
Very recently, chip designs have started to use vertical field-effect transistors to help increase the number of transistors that can fit on a chip without having to substantially increase the overall chip size. For example, by using vertical transistor structures, it can increase the on chip finFET-equivalent density along a plane parallel to the semiconductor substrate. Vertical transport architecture FET devices include source/drain regions at ends of the fins on top and bottom sides of the fins so that current flows through the fins in a vertical direction (e.g., perpendicular to the semiconductor substrate) between a bottom source/drain region and a top source/drain region.
As chip designs continue to further miniaturize on-chip device dimensions, such designs attempt to locate vertical FETs closer and closer to each other on a semiconductor chip to enhance the feature density. The distance between a feature on a fin and the same feature on an adjacent fin is the pitch of the pattern of fins on a chip. As vertical FETs are located closer to each other, the respective fins of adjacent vertical FETs are separated from each other by smaller pitch values and tighter pitch tolerances (pitch variability), to meet chip design requirements. As pitch values between adjacent fins become smaller, conventional fabrication technologies such as 193i optical lithography concede that a single lithographic exposure (also referred to as “direct print” lithography) is not capable of providing sufficient resolution in order to meet the higher feature density requirements.
Conventional semiconductor fabrication processes have attempted to enhance the feature density by using fabrication technologies that involve multiple-patterning (or multi-patterning) such as Self-Aligned Double Patterning (SADP), and Self-Aligned Quadruple Patterning (SAQP). The minimum pitch for a single 193i optical lithographic exposure is recognized to be limited to 76 nm. SADP and SAQP techniques utilize multiple depositions and etch processes, to attempt to increase the feature density. For example, with the SAQP technique a 19 nm pitch (i.e., 76 nm divided by 4) is now accessible in principle.
Process variability in the multiple patterning processes leads to errors such as pitch-walk, which are excursions of the pitch from the nominal value. Pitch walk can also accumulate tolerance errors over multiple sequential pairs of adjacent fins.
Though state-of-the-art direct print lithography techniques (direct print lithography inherently has zero pitch walk) such as extreme ultra-violet (EUV) lithography (13.5 nm wavelength) can pattern much smaller pitches than the 76 nm achievable by 193i optical lithography, there are still some drawbacks such as the duty cycles for a given process formulation. The term “duty cycle” defines the spacing between lines (features) relative to the width of the lines (features) in the critical dimension, expressed as a ratio. Smaller duty cycles such as 1:5 (line width of 1 part to a space width of 5 parts at pitches smaller than 76 nm) are still a challenge to fabricate using any available direct print technology. That is, typical semiconductor fabrication applications have been limited to regular width lines separated by spaces of regular width that is equal to the regular width of the lines (i.e., a 1:1 duty cycle).
Therefore, the inventors have discovered that there is a need for a new fabrication method of semiconductor structures to fabricate patterns of low duty cycle (thin lines flanked by large spaces) with zero tolerance on pitch variability (pitch walk).